FM38F16SBB-9MGD_4G bits DDR3L SDRAM
DDR3L SDRAM (1.35V) is a low voltage version of theDDR3 (1.5V)SDRAM.Referto the DDR3 (1.5V) SDRAM data sheet specifications when running in 1.5V compatible mode
  • VDD = VDDQ = 1.35V (1.283–1.45V)
  • Backward compatible to VDD = VDDQ = 1.5V ±0.075V
  • patible in 1.5V applications
  • Commercial (0°C ≤TC ≤ +95°C)
详细内容


Description

DDR3L SDRAM(1.35V)is a low voltage version of theDDR3(1.5V)SDRAM.Referto the DDR3(1.5V)SDRAM data sheet specifications when running in 1.5V compatible mode.

Features

•VDD=VDDQ=1.35V(1.283–1.45V)

•Backward compatible to VDD=VDDQ=1.5V±0.075V

–Supports DDR3L devices to be backward compatible in 1.5V applications

•Differentialbidirectionaldatastrobe

•8n-bit prefetch architecture

•Differential clock inputs(CK,CKB)

•8 internalbanks

•Nominal and dynamic on-die termination(ODT)

for data,strobe,and mask signals

•Programmable CAS(READ)latency(CL)

•Programmable posted CAS additive latency(AL)

•Programmable CAS(WRITE)latency(CWL)

•Fixed burst length(BL)of 8 and burst chop(BC)of 4

(via the mode register set[MRS])

•Selectable BC4 or BL8 on-the-fly(OTF)

•Self refresh mode

•TC of 0°C to+95°C

–64ms,8192-cycle refresh at 0°C to+85°C

–32ms at+85°C to+95°C

•Self refresh temperature(SRT)

•Automatic self refresh(ASR)

•Writeleveling

•Multipurposeregister

•Outputdrivercalibration

Options

•Configuration

–512 Meg x 8

–256 Meg x 16

•FBGA package(Pb-free)–x8

–78-ball(10.6mm x 7.5mm)

•FBGA package(Pb-free)–x16

–96-ball(13.5mm x 7.5mm)

•Timing–cycle time

–938ps CL=14(DDR3-2133)

–1.07ns CL=13(DDR3-1866)

–1.25ns CL=11(DDR3-1600)

•Operating temperature

–Commercial(0°C≤TC≤+95°C)